Exercise5_schematic_5_3.asc is a single-transistor stage with a three-section RC network (47 nF / 4.7 kΩ), with the input amplitude stepped from 10 mV to 50 mV. It was part of the submission but isn't ...
AayushKasliwal LTspice-Simulations Code Issues Pull requests Actions Projects Security and quality Insights More items main LTspice-Simulations / 07_BJT_CE_Amplifier / ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results